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LTC2273/ltc2272 1 22732f typical application features applications description 16-bit, 80msps/65msps serial output adc the ltc ? 2273/ltc2272 are 80msps/65msps, 16-bit a/d converters with a high speed serial interface. they are designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700mhz. the input range of the adc can be optimized using the pga front end. the output data is serialized according to the jedec serial interface for data converters speci? cation (jesd204). the LTC2273/ltc2272 are perfect for demanding applica- tions where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. the ac performance includes a 77.7db noise floor and 100db spurious free dynamic range (sfdr). ultra low internal jitter of 80fs rms allows undersampling of high input frequencies with excellent noise performance. maximum dc specs include 4.5lsb inl and 1lsb dnl (no missing codes) over temperature. the encode clock inputs, enc + and enc C , may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. a clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n high speed serial interface (jesd204) n sample rate: 80msps/65msps n 77.7dbfs noise floor n 100db sfdr n sfdr >90db at 140mhz (1.5v p-p input range) n pga front end (2.25v p-p or 1.5v p-p input range) n 700mhz full power bandwidth s/h n optional internal dither n single 3.3v supply n power dissipation: 1100mw/990mw n clock duty cycle stabilizer n pin compatible family 105msps: ltc2274 80msps: LTC2273 65msps: ltc2272 n 40-pin 6mm 6mm qfn package n telecommunications n receivers n cellular base stations n spectrum analysis n imaging systems n ate C + s/h amp correction logic 8b/10b encoder 16-bit pipelined adc core internal adc reference generator 1.25v common mode bias voltage clock/duty cycle control scrambler/ pattern generator pll 20x enc + enc C v cm analog input 22732 ta01 sync + sync C ov dd 3.3v 1.2v to 3.3v 3.3v fam asic or fpga sense clock 2.2f pat1 pat0 srr1 srr0 scram shdn msbinv dith pga 0.1f 0.1f 0.1f v dd gnd a in + a in C cmlout + cmlout C 16 20 C + serializer serial receiver 50 50 128k point fft, f in = 4.93mhz, C1dbfs, pga = 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g04 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0
LTC2273/ltc2272 2 22732f pin configuration absolute maximum ratings supply voltage (v dd ) ................................... C0.3v to 4v analog input voltage (note 3) .......C0.3v to (v dd + 0.3v) digital input voltage ......................C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation .............................................2000mw operating temperature range LTC2273c/ltc2272c ............................... 0c to 70c LTC2273i/ltc2272i .............................. C40c to 85c storage temperature range ................... C65c to 150c digital output supply voltage (ov dd ) .......... C0.3v to 4v ov dd = v dd (notes 1, 2) 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 uj package 40-lead (6mm s 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 v dd v dd gnd a in + a in C gnd gnd gnd enc + enc C gnd sync C sync + gnd gnd ov dd cmlout + cmlout C ov dd gnd gnd v cm sense gnd msbinv pga scram pat1 pat0 fam gnd v dd v dd gnd dith ismode srr0 srr1 shdn shdn 21 30 10 1 t jmax = 150c, ja = 22c/w exposed pad (pin 41) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC2273cuj#pbf LTC2273cuj#trpbf LTC2273uj 40-lead (6mm 6mm) plastic qfn 0c to 70c LTC2273iuj#pbf LTC2273iuj#trpbf LTC2273uj 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2272cuj#pbf ltc2272cuj#trpbf ltc2272uj 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2272iuj#pbf ltc2272iuj#trpbf ltc2272uj 40-lead (6mm 6mm) plastic qfn C40c to 85c lead based finish tape and reel part marking* package description temperature range LTC2273cuj LTC2273cuj#tr LTC2273uj 40-lead (6mm 6mm) plastic qfn 0c to 70c LTC2273iuj LTC2273iuj#tr LTC2273uj 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2272cuj ltc2272cuj#tr ltc2272uj 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2272iuj ltc2272iuj#tr ltc2272uj 40-lead (6mm 6mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ converter characteristics symbol conditions min typ max units integral linearity error differential analog input (note 5) t a = 25c 1.2 4 lsb integral linearity error differential analog input (note 5) l 1.5 4.5 lsb differential linearity error differential analog input l 0.3 1 lsb offset error (note 6) l 1 8.5 mv offset drift 10 v/c gain error external reference l 0.2 1.5 %fs full-scale drift internal reference external reference 30 15 ppm/c ppm/c transition noise 3lsb rms the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
LTC2273/ltc2272 3 22732f analog input the l denotes denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v l 1.5 or 2.25 v p-p v in, cm analog input common mode differential input (note 7) l 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd (note 10) l C1 1 a i sense sense input leakage current 0v sense v dd (note 11) C3 3 a c in analog input capacitance sample mode enc + < enc C hold mode enc + > enc C 6.7 1.8 pf pf t ap sample-and-hold acquisition delay time 1ns t jitter sample-and-hold acquisition delay time jitter 80 fs rms cmrr analog input common mode rejection ratio 1v < (a in + = a in C ) <1.5v 80 db bw-3db full power bandwidth r s 25 700 mhz dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol param eter conditions LTC2273 ltc2272 units min typ max min typ max snr signal-to-noise ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 77.6 75.4 77.6 75.4 dbfs dbfs 15mhz input (2.25v range, pga = 0), t a = 25c 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) l 76.5 76.2 77.5 77.2 75.3 76.5 76.2 77.5 77.2 75.3 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1), t a = 25c 70mhz input (1.5v range, pga = 1) l 74.5 74.2 77.2 75.1 74.8 74.5 74.2 77.2 75.1 74.8 dbfs dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 76.3 74.5 76.3 74.5 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 75.9 74.3 75.9 74.3 dbfs dbfs sfdr spurious free dynamic range 2 nd or 3 rd harmonic 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 100 100 100 100 dbc dbc 15mhz input (2.25v range, pga = 0), t a = 25c 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) l 85 84 95 95 100 85 84 95 95 100 dbc dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1), t a = 25c 70mhz input (1.5v range, pga = 1) l 84 83 86 94 92 84 83 86 94 92 dbc dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 85 90 85 90 dbc dbc 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 80 85 80 85 dbc dbc
LTC2273/ltc2272 4 22732f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs unless otherwise noted. (note 4) dynamic accuracy symbol param eter conditions LTC2273 ltc2272 units min typ max min typ max sfdr spurious free dynamic range 4 th harmonic or higher 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 100 100 100 100 dbc dbc 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) l 90 100 100 90 100 100 dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) l 90 100 100 90 100 100 dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 95 100 95 100 dbc dbc 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 90 95 90 95 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 77.5 75.3 77.5 75.3 dbfs dbfs 15mhz input (2.25v range, pga = 0), t a = 25c 15mhz input (2.25v range, pga = 0 15mhz input (1.5v range, pga = 1) l 76.3 75.9 77.4 77 75.2 76.3 75.9 77.4 77 75.2 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1), t a = 25c 70mhz input (1.5v range, pga = 1) l 74.4 74.1 76.7 75 74.7 74.4 74.1 76.7 75 74.7 dbfs dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 75.3 74.3 75.3 74.3 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 73.4 73.4 73.4 73.4 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither off 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 100 100 100 100 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 100 100 100 100 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither on 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) l 97 115 115 97 115 115 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 110 110 110 110 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs
LTC2273/ltc2272 5 22732f the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) common mode bias characteristics parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 l 40 ppm/c v cm line regulation 3.135v v dd 3.465v l 1mv/v v cm output resistance C1ma | i out | 1ma l 2 symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 7) l 0.2 v v icm common mode input voltage internally set externally set (note 7) 1.4 1.6 3.0 v r in input resistance (see figure 2) 6 k c in input capacitance 3pf sync inputs ( sync + , sync C ) v sid sync differential input voltage (note 7) l 0.2 v v sicm sync common mode input voltage internally set externally set (note 7) 1.1 1.6 2.2 v r sin sync input resistance 16.5 k c sin sync input capacitance 3pf logic inputs (dith, pga, msbinv, scram, fam, shdn, srr1, srr0, ismode, pat1, pat0) v ih high level input voltage v dd = 3.3v l 2v v il low level input voltage v dd = 3.3v l 0.8 v i in input current v in = 0v to v dd l 10 a c in input capacitance 1.5 pf high-speed serial outputs (cmlout + , cmlout C ) v oh output high level directly-coupled 50 to ov dd directly-coupled 100 differential ac-coupled ov dd ov dd C 0.2 ov dd C 0.2 v v v v ol output low level directly-coupled 50 to ov dd directly-coupled 100 differential ac-coupled ov dd C 0.4 ov dd C 0.6 ov dd C 0.6 v v v v ocm output common mode voltage directly-coupled 50 to ov dd directly-coupled 100 differential ac-coupled ov dd C 0.2 ov dd C 0.4 ov dd C 0.4 v v v r out output resistance single-ended differential l 35 50 100 65 the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) digital inputs and digital outputs
LTC2273/ltc2272 6 22732f timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 105mhz differential enc + /enc C = 2v p-p sine wave with 1.6v common mode, input range = 2.25v p-p with differential drive (pga = 0), unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C1/2lsb when the output code ? ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: v dd = 3.3v, f sample = 80msps (LTC2273) or 65msps (ltc2272) input range = 2.25v p-p with differential drive. note 9: recommended operating conditions. note 10: the dynamic current of the switched capacitors analog inputs can be large compared to the leakage current and will vary with the sample rate. note 11: leakage current will have higher transient current at power up. keep drive resistance at or below 1k. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) power requirements symbol param eter conditions LTC2273 ltc2272 units min typ max min typ max v dd analog supply voltage l 3.135 3.3 3.465 3.135 3.3 3.465 v p shdn shutdown power shdn = v dd 55mw ov dd output supply voltage cmlout directly-coupled, 50 to ov dd (note 7) cmlout directly-coupled, 100 diff. (note 7) cmlout ac-coupled (note 7) l 1.2 1.4 1.4 v dd v dd v dd 1.2 1.4 1.4 v dd v dd v dd v v v i vdd analog supply current dc input l 233 370 300 340 ma i ovdd output supply current cmlout directly-coupled, 50 to ov dd cmlout directly-coupled, 100 diff. cmlout ac-coupled l 8 16 16 8 16 16 ma ma ma p dis power dissipation dc input l 1100 1221 990 1122 mw symbol param eter conditions LTC2273 ltc2272 units min typ max min typ max f s sampling frequency (note 9) l 20 80 20 65 mhz t conv conversion period 1/f s 1/f s s t l enc clock low time (note 7) l 4.06 6.25 25 5.03 7.69 25 ns t h enc clock high time (note 7) l 4.06 6.25 25 5.03 7.69 25 ns t ap sample-and-hold aperture delay 0.7 0.7 ns t bit , ui period of a serial bit t conv /20 t conv /20 s t jit total jitter of cmlout (p-p) ber = 1eC12 (note 7) l 0.35 0.35 ui t r , t f differential rise and fall time of cmlout (20% to 80%) r term = 50, c l = 2pf (note 7) l 50 110 50 110 ps t su sync to enc clock setup time (note 7) l 22ns t hd enc clock to sync hold time (note 7) l 2.5 2.5 ns t cs enc clock to sync delay (note 7) l t hd t conv C t su t hd t conv C t su ns lat p pipeline latency 9 9 cycles lat sc latency from sync active to comma out 3 3 cycles lat sd latency from sync release to data out 2 2 cycles
LTC2273/ltc2272 7 22732f n C 6 n C 10 n C 9 n C 8 n C 1 n n C 5 n C 4 n + 3 n + 4 n C 9 n C 8 n C 7 n n + 1 t h t conv lat p t l t ap t bit n n + 1 n + 2 n + 8 n + 9 22732 td01 n + 10 analog input enc + internal parallel data internal 8b/10b data cmlout + /cmlout C timing diagrams n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n ? 10 n ? 9 n ? 8 n ? 7 k28.5 (x2) k28.5 (x2) t conv t cs(max) lat sc t hd t cs(min) t su analog input enc + sync + cmlout + /cmlout C 22732 td02 n ? 1 n n + 1 n + 2 n + 3 n + 4 k28.5 (x2) k28.5 (x2) k28.5 (x2) n ? 7 n ? 6 t conv t cs(max) lat sd t hd t cs(min) t su analog input enc + cmlout + /cmlout C 22732 td03 sync + analog input to serial data out timing sync + falling edge to comma (k28.5) timing sync + rising edge to data timing
LTC2273/ltc2272 8 22732f LTC2273: differential non- linearity (dnl) vs output code LTC2273: ac grounded input histogram LTC2273: 128k point fft, f in = 5.1mhz, C1dbfs, pga = 0 LTC2273: 64k point fft, f in = 14.8mhz, C1dbfs, pga = 0 LTC2273: 64k point fft, f in = 14.8mhz, C10dbfs, pga = 0 LTC2273: sfdr vs input level, f in = 15mhz, pga = 0, dither on LTC2273: 64k point 2-tone fft, f in = 14.01mhz and 15.81mhz, C7dbfs, pga = 0 LTC2273: integral non-linearity (inl) vs output code LTC2273: sfdr vs input level, f in = 15mhz, pga = 0, dither off output code 0 inl error (lsb) 16384 32768 49152 22732 g01 65536 C2.0 C1.5 C1.0 C0.5 0.0 0.5 1.0 1.5 2.0 output code 0 dnl error (lsb) 16384 32768 49152 22732 g02 65536 C1.0 C0.8 C0.6 C0.4 C0.2 0.0 0.2 0.4 0.6 0.8 1.0 output code 32769 count 32779 32789 22732 g03 32799 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g04 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g05 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g06 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g09 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g07 30 40 50 60 70 80 90 100 110 120 130 140 v dd = 3.3v, ov dd = 1.5v, t a = 25c, f s = 80msps, unless otherwise noted. input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g08 30 40 50 60 70 80 90 100 110 120 130 140 typical performance characteristics
LTC2273/ltc2272 9 22732f typical performance characteristics LTC2273: 64k point 2-tone fft, f in = 14.01mhz and 15.8mhz, C15dbfs, pga = 0 LTC2273: 64k point fft, f in = 70mhz, C1dbfs, pga = 0 LTC2273: 64k point fft, f in = 70mhz, C1dbfs, pga = 1 LTC2273: 128k point fft, f in = 70mhz, C20dbfs, pga = 0, dither off LTC2273: 128k point fft, f in = 70mhz, C20dbfs, pga = 0, dither on LTC2273: 64k point fft, f in = 140.2mhz, C1dbfs, pga = 1 LTC2273: sfdr vs input level, f in = 140mhz, pga = 1, dither off LTC2273: sfdr vs input level, f in = 140mhz, pga = 1, dither on LTC2273: 64k point fft, f in = 170.2mhz, C1dbfs, pga = 1 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g10 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g11 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g12 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g13 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g14 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g15 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g16 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g17 30 40 50 60 70 80 90 100 110 120 130 140 frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g18 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 v dd = 3.3v, ov dd = 1.5v, t a = 25c, f s = 80msps, unless otherwise noted.
LTC2273/ltc2272 10 22732f sample rate (msps) 20 iv dd (ma) 70 45 95 120 22732 g25 240 280 320 360 400 v dd = 3.3v v dd = 3.47v v dd = 3.13v typical performance characteristics LTC2273: 64k point fft, f in = 250.2mhz, C1dbfs, pga = 1 LTC2273: sfdr vs input frequency LTC2273: snr vs input frequency LTC2273: snr and sfdr vs sample rate, f in = 5.1mhz LTC2273: snr and sfdr vs supply voltage (v dd ), f in = 5.2mhz LTC2273: sfdr vs analog input common mode voltage, 5mhz and 70mhz, C1dbfs LTC2273: iv dd vs sample rate, 5mhz sine, C1dbfs frequency (mhz) 0 amplitude (dbfs) 10 20 30 40 22732 g19 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 input frequency (mhz) 0 sfdr (dbc) 200 22732 g20 400 300 100 pga = 1 pga = 0 65 70 75 80 85 90 95 100 105 input frequency (mhz) 0 snr (dbfs) 200 22732 g21 400 300 100 pga = 1 pga = 0 70 72 74 76 78 sample rate (msps) 20 snr (dbfs) and sfdr (dbc) 100 60 22732 g22 120 80 40 sfdr snr 70 75 80 85 90 95 100 105 110 supply voltage (v) 2.8 snr and sfdr (dbfs) 3.2 22732 g23 3.4 3.0 sfdr snr 70 75 80 85 90 95 100 105 110 analog input common mode voltage (v) 0.50 sfdr (dbc) 0.75 1.00 1.25 1.50 1.75 22732 g24 2.00 60 65 70 75 80 85 90 95 100 105 110 5mhz 70mhz v dd = 3.3v, ov dd = 1.5v, t a = 25c, f s = 80msps, unless otherwise noted.
LTC2273/ltc2272 11 22732f typical performance characteristics ltc2272: differential non- linearity (dnl) vs output code ltc2272: ac grounded input histogram ltc2272: 128k point fft, f in = 5.1mhz, C1dbfs, pga = 0 ltc2272: 64k point fft, f in = 14.8mhz, C1dbfs, pga = 0 ltc2272: 64k point fft, f in = 14.8mhz, C10dbfs, pga = 0 ltc2272: sfdr vs input level, f in = 15mhz, pga = 0, dither on ltc2272: 64k point 2-tone fft, f in = 14.01mhz and 15.8mhz, C7dbfs, pga = 0 ltc2272: integral non-linearity (inl) vs output code ltc2272: sfdr vs input level, f in = 15mhz, pga = 0, dither off output code 0 inl error (lsb) 16384 32768 49152 22732 g26 65536 C2.0 C1.5 C1.0 C0.5 0.0 0.5 1.0 1.5 2.0 output code 0 dnl error (lsb) 16384 32768 49152 22732 g27 65536 C1.0 C0.8 C0.6 C0.4 C0.2 0.0 0.2 0.4 0.6 0.8 1.0 output code 32894 count 32904 32914 22732 g28 32924 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 frequency (mhz) 0 amplitude (dbfs) 10 20 30 22732 g29 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 frequency (mhz) amplitude (dbfs) 22732 g30 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 frequency (mhz) amplitude (dbfs) 22732 g31 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 frequency (mhz) amplitude (dbfs) 22732 g34 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g32 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g33 30 40 50 60 70 80 90 100 110 120 130 140 v dd = 3.3v, ov dd = 1.5v, t a = 25c, f s = 65msps, unless otherwise noted.
LTC2273/ltc2272 12 22732f typical performance characteristics ltc2272: 64k point fft, f in = 14.01mhz and 15.8mhz, C15dbfs, pga = 0 ltc2272: 64k point fft, f in = 70mhz, C1dbfs, pga = 0 ltc2272: 64k point fft, f in = 70mhz, C1dbfs, pga = 1 ltc2272: 128k point fft, f in = 70mhz, C20dbfs, pga = 0, dither off ltc2272: 128k point fft, f in = 70mhz, C20dbfs, pga = 0, dither on ltc2272: 64k point fft, f in = 140.2mhz, C1dbfs, pga = 1 ltc2272: sfdr vs input level, f in = 140mhz, pga = 1, dither off ltc2272: sfdr vs input level, f in = 140mhz, pga = 1, dither on ltc2272: 64k point fft, f in = 170.2mhz, C1dbfs, pga = 1 frequency (mhz) amplitude (dbfs) 22732 g35 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 frequency (mhz) amplitude (dbfs) 22732 g36 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0102030 frequency (mhz) amplitude (dbfs) 22732 g37 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0102030 frequency (mhz) amplitude (dbfs) 22732 g38 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 frequency (mhz) amplitude (dbfs) 22732 g39 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 frequency (mhz) amplitude (dbfs) 22732 g40 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g41 30 40 50 60 70 80 90 100 110 120 130 140 input level (dbfs) C80 sfdr (dbc and dbfs) C70 C60 C50 C40 C30 C20 C10 0 22732 g42 30 40 50 60 70 80 90 100 110 120 130 140 frequency (mhz) amplitude (dbfs) 22732 g43 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 v dd = 3.3v, ov dd = 1.5v, t a = 25c, f s = 65msps, unless otherwise noted.
LTC2273/ltc2272 13 22732f sample rate (msps) 20 iv dd (ma) 60 40 80 100 22732 g50 240 280 320 360 v dd = 3.3v v dd = 3.47v v dd = 3.13v typical performance characteristics ltc2272: 64k point fft, f in = 250.2mhz, C1dbfs, pga = 1 ltc2272: sfdr vs input frequency ltc2272: snr vs input frequency ltc2272: snr and sfdr vs sample rate, f in = 5.2mhz ltc2272: snr and sfdr vs supply voltage (v dd ), f in = 5.2mhz ltc2272: sfdr vs analog input common mode voltage, 5mhz and 70mhz, C1dbfs ltc2272: iv dd vs sample rate, 5mhz sine, C1dbfs frequency (mhz) amplitude (dbfs) 22732 g44 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 0 102030 input frequency (mhz) 0 sfdr (dbc) 200 22732 g45 400 300 100 65 70 75 80 85 90 95 100 110 105 input frequency (mhz) 0 snr (dbfs) 200 22732 g46 400 300 100 70 72 74 76 78 sample rate (msps) 20 snr (dbfs) and sfdr (dbc) 60 22732 g47 100 80 40 sfdr snr 70 75 80 85 90 95 100 105 110 supply voltage (v) 2.8 snr and sfdr (dbfs) 3.2 22732 g48 3.4 3.0 sfdr snr 70 75 80 85 90 95 100 105 110 analog input common mode voltage (v) 0.50 sfdr (dbc) 0.75 1.00 1.25 1.50 1.75 22732 g49 2.00 60 65 70 75 80 85 90 95 100 105 110 5mhz 70mhz v dd = 3.3v, ov dd = 1.5v, t a = 25c, f s = 65msps, unless otherwise noted.
LTC2273/ltc2272 14 22732f typical performance characteristics cmlout dual-dirac ber bathtub curve, 400mbps cmlout dual-dirac ber bathtub curve, 1.3gbps cmlout dual-dirac ber bathtub curve, 1.6gbps cmlout eye diagram 400mbps cmlout eye diagram 1.3gbps cmlout eye diagram 1.6gbps v dd = 3.3v, ov dd = 1.5v, t a = 25c, unless otherwise noted. unit interval (ui) 0 bit error rate (ber) 0.8 0.4 22732 g51 1.0 0.6 0.2 1.0eC14 1.0eC12 1.0e C 10 1.0eC08 1.0eC06 1.0eC04 1.0eC02 1.0e+00 unit interval (ui) 0 bit error rate (ber) 0.8 0.4 22732 g52 1.0 0.6 0.2 1.0eC14 1.0eC12 1.0e C 10 1.0eC08 1.0eC06 1.0eC04 1.0eC02 1.0e+00 unit interval (ui) 0 bit error rate (ber) 0.8 0.4 22732 g53 1.0 0.6 0.2 1.0eC14 1.0eC12 1.0e C 10 1.0eC08 1.0eC06 1.0eC04 1.0eC02 1.0e+00 416.7ps/div 22732 g54 100mv/div 128.2ps/div 22732 g55 100mv/div 104.2ps/div 22732 g56 100mv/div
LTC2273/ltc2272 15 22732f pin functions v dd (pins 1, 2, 12, 13 ): analog 3.3v supply. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 3, 6, 7, 8, 11, 14, 21, 26, 27, 30, 37, 40, 41): adc power ground. a in + (pin 4): positive differential analog input. a in C (pin 5): negative differential analog input. enc + (pin 9): positive differential encode input. the sampled analog input is held on the rising edge of enc + . this pin is internally biased to 1.6v through a 6.2k resistor. output data can be latched on the falling edge of enc + . enc C (pin 10): negative differential encode input. the sampled analog input is held on the falling edge of enc-. this pin is internally biased to 1.6v through a 6.2k resistor. bypass to ground with a 0.1uf capacitor for a single-ended encode signal. dith (pin 15): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. ismode (pin 16): idle synchronization mode. when is- mode is not asserted, synchronization is performed with a series of commas (k28.5). when ismode is asserted, a special idle sync mode is enabled where synchroniza- tion is performed by sending a comma (k28.5) followed by the appropriate data code-group (d5.6 or d16.2) for establishing a negative running disparity for the ? rst data code-group after synchronization. srr0 (pin 17): sample rate range select bit0. used with the srr1 pin to select the sample rate operating range. srr1 (pin 18): sample rate range select bit1. used with the srr0 pin to select the sample rate operating range. shdn (pins 19, 20): shutdown pins. a high level on both pins will shut down the chip. a low level is required for normal operation. ov dd (pins 22, 25): positive supply for the output driv- ers. typically 1.2v to 3.3v. the minimum supply is 1.4v when applying a differential termination on the cmlout pins or when ac-coupling the cmlout pins. bypass to ground with 0.1f ceramic chip capacitor. cmlout C (pin 23): negative high-speed cml output. cmlout + (pin 24): positive high-speed cml output. sync + (pin 28): sync request positive input (active low for compatibility with jesd204). a low level on this pin for at least two sample clock cycles will initiate frame synchronization. sync C (pin 29): sync request negative input. a high level on this pin for at least two sample clock cycles will initiate frame synchronization. for single-ended operation, bypass to ground with a 0.1f capacitor and use sync + as the sync point.
LTC2273/ltc2272 16 22732f fam (pin 31): frame alignment monitor enable. a high level enables the substitution of predetermined data at the end of the frame with a k28.7 symbol for frame alignment monitoring. pat0 (pin 32): pattern select bit0. use with pat1 to select a test pattern for the serial interface. pat1 (pin 33): pattern select bit1. use with pat0 to select a test pattern for the serial interface. scram (pin 34): enable data scrambling. a high level on this pin will apply the polynomial 1 + x 14 + x 15 in scram- bling each adc data sample. the scrambling takes place before the 8b/10b encoding. pga (pin 35): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.25v p-p . high selects a front-end gain of 1.5, input range of 1.5v p-p . msbinv (pin 36): invert the msb. a high level will invert the msb to enable the 2s compliment format. sense (pin 38): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.25v (pga = 0). v cm (pin 39): 1.25v output. optimum voltage for input common mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recom- mended. gnd (exposed pad) (pin 41): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. pin functions
LTC2273/ltc2272 17 22732f correction logic 8b/10b encoder scrambler/ pattern generator pll 20x clk v cm 22732 bd sync + sync C pat1 pat0 srr1 srr0 scram v dd ov dd gnd cmlout + cmlout C 20 serializer control logic msbinv shdn dith pga clock driver with duty cycle control 2.5v reference adc reference 1x or 2x 0.5x reference control enc C enc + fam sense 16 C + dither signal generator s/h and pga a in C a in + first stage second stage third stage pipelined adc stages fourth stage fifth stage block diagram figure 1. functional block diagram
LTC2273/ltc2272 18 22732f definitions dynamic performance terms signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = C20log ( (v 2 2 + v 3 2 + v 4 2 + ... v n 2 )/v 1 ) where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3rd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de? ned as the ratio of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample- and-hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) serial interface terms 8b/10b encoding a data encoding method designed to make an 8-bit data word (octet) more suitable for serial transmission. the resulting 10-bit word (code-group) has two fundamental strengths: 1) the receiver does not require a high-speed clock to capture the data. this is because the output code-groups are run-length limited, ensuring that there are enough transitions in the bit stream for the receiver to lock onto the data and recover the high-speed clock. 2) ac coupling is permitted because the code-groups are generated in a way that ensures the data stream is dc balanced (see running disparity). a table of the 256 possible input octets with the resulting 10-bit code-groups is documented in ieee std 802.3-2002 part3 table 36-1. the name associated with each of the 256 data code-groups is formatted dx.y, with x ranging from 0 to 31 and y ranging from 0 to 7. table 36-2 of
LTC2273/ltc2272 19 22732f definitions the standard de? nes an additional set of 12 special code- groups for non-data characters such as commas. special code-group names begin with k instead of d. a complete 8b/10b description is found in clause 36.2 of ieee std 802.3-2002 part3. current mode logic (cml) a technique used to implement differential high-speed logic. cml employs differential pairs (usually n-type) to steer current into resistive loads. it is possible to implement any logic function using cml. the output swing and offset is dependant on the bias current, the load resistance, and termination resistance. this product family uses cml drivers to transmit high- speed serial data to the outside world. the output driver bias current is typically 16ma, generating a signal swing potential of 400mv p-p (800mv p-p diff.) across the com- bined internal and external termination resistance of 25 on each output. code-group the 10-bit output from an 8b/10b encoder or the 10-bit input to the 8b/10b decoder. comma a special 8b/10b code-group containing the binary se- quence 0011111 or 1100000. commas are used for frame alignment and synchronization because a comma sequence cannot be generated by any combination of normal code-groups (unless a bit error occurs). there are three special code-groups that contain a comma, k28.1, k28.5, and k28.7. for brevity, each of these three special code-groups are often called a comma, but in the strictest sense it is the ? rst 7 bits of these code-groups that are designated a comma. dc balanced signal a specially conditioned signal that may be ac coupled with minimal degradation to the signal. dc balance is achieved when the average number of 1s and 0s are equal, eliminat- ing the undesirable effects of dc wander on the receive side of the coupling capacitor. when 8b/10b coding is used, dc balance is achieved by following disparity rules (see running disparity). de-scrambler a logic block that restores scrambled data to its pre- scrambled state. a self aligning de-scrambler is based on the same pseudo random bit sequence as the scrambler, so it requires no alignment signals. in this product family the scrambler is based on the 1 + x 14 + x 15 polynomial, and the self aligning process results in an initial loss of one adc sample. frame a group of octets or code-groups that make up one complete word. for this product family, a frame consists of two complete octets or code-groups, and constitutes one adc sample. frame alignment monitoring (fam) after initial frame synchronization has been established, frame alignment monitoring enables the receiver to verify that code-group alignment is maintained without the loss of data. this is done by substituting a k28.7 comma for the last code-group of the frame when certain conditions are met. the receiver uses this comma as a position marker within the frame for alignment veri? cation. after decoding the data, the receiver replaces the k28.7 comma with the original data. idle frame synchronization mode (ismode) a special synchronization mode where idle ordered sets are used to establish initial frame synchronization instead of k28.5 commas. an idle ordered set is de? ned in the ieee std 802.3-2002 part3, clause 36.2.4.12. in general, it is a k28.5 comma followed by either a d5.6 or a d16.2. if the running dispar- ity after the transmission of the k28.5 comma is positive,
LTC2273/ltc2272 20 22732f definitions a d16.2 will be transmitted after the comma, otherwise a d5.6 will be transmitted. the result is that the ending disparity of an idle ordered set will always be negative. initial frame synchronization the process of communicating frame synchroniza-tion information to the receiver upon the request of the receiver. for jesd204 compliance, k28.5 commas are transmitted as the preamble. once the preamble has been detected the receiver terminates the synchronization request, and the preamble transmission continues until the end of the frame. the receiver designates the ? rst normal data word after the preamble to be the start of the data frame. octet the 8-bit input to an 8b/10b encoder, or the 8-bit output from an 8b/10b decoder. run-length limited (rll) the result of limiting the number of consecutive 1s or 0s in a data stream by encoding the data prior to serial transmission. this process guarantees that there will be an adequate number of transitions in the serial data for the receiver to lock onto with a phase-locked loop and recover the high-speed clock. running disparity in order to maintain dc balance there are two possible 8b/10b output code-groups for each input octet. the running disparity is calculated to determine which of the two code-groups should be transmitted to maintain dc balance. the disparity of a code-group is analyzed in two segments called sub-blocks. sub-block1 consists of the ? rst six bits of a code-group and sub-block2 consists of the last four bits of a code-group. when a sub-block is more heavily weighted with 1s the running disparity is positive, and when it is more heavily weighted with 0s the running disparity is negative. when the number of 1s and 0s are equal in a sub-block, the running disparity remains unchanged. the polarity of the current running disparity determines which code-group should be transmitted to maintain dc balance. for a complete description of disparity rules, refer to ieee std 802.3-2002 part3, clause 36.2.4.4. pseudo random bit sequence (prbs) a data sequence having a random nature over a ? nite interval. the most commonly used prbs test patterns may be described by a polynomial in the form of 1 + x m + x n and have a random nature for the length of up to 2 n C 1 bits, where n indicates the order of the prbs polynomial and m plays a role in maximizing the length of the random sequence. scrambler a logic block that applies a pseudo random bit sequence to the input octets to minimize the tonal content of the high-speed serial bit stream.
LTC2273/ltc2272 21 22732f applications information converter operation the core of the LTC2273/ltc2272 are cmos pipelined multi-step converters with a front-end pga. as shown in figure 1, the converter has ? ve pipelined adc stages. a sampled analog input will result in a digitized value nine clock cycles later (see the timing diagram section). the analog input (a in + , a in C ) is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. the encode clock input (enc + , enc C ) is also differential for improved common mode noise immunity. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac, and an error residue ampli? er. the function of each stage is to produce a digital representation of its input voltage along with the resulting analog error residue. the adc of each stage provides the quantization, and the residue is produced by taking the difference between the input voltage and the output of the reconstruction dac. the residue is ampli? ed by the residue ampli? er and passed on to the next stage. the successive stages of the pipeline operate on alternating phases of the clock so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. the pipelined adc of the LTC2273/ltc2272 has two phases of operation determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. when enc is low, the analog input is sampled differentially onto the input sample-and-hold capacitors, inside the s/h & pga block of figure 1. on the rising edge of enc, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the high phase of enc. on the falling edge of enc, the ? rst stage produces its residue which is acquired by the second stage. the process continues to the end of the pipeline. each adc stage following the ? rst has additional error correction range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being encoded, serialized, and sent to the output buffer.
LTC2273/ltc2272 22 22732f applications information sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the LTC2273/ ltc2272 cmos differential sample and hold. the differ- ential analog inputs are sampled directly onto sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track, the differential input voltage. on the rising edge of enc, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input should swing 0.5625v for the 2.25v range (pga = 0) or 0.375v for the 1.5v range (pga = 1), around a common mode volt- age of 1.25v. the v cm output pin (pin 39) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedance as with all high performance, high speed adcs the dynamic performance of the LTC2273/ltc2272 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and in- put reactance can in? uence sfdr. at the falling edge of enc the sample-and-hold circuit will connect the 4.9pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, hold- ing the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. c sample 4.9pf v dd v dd LTC2273/ltc2272 a in + 22732 f02 c sample 4.9pf v dd a in C enc C enc + 1.6v 6k 1.6v 6k c parasitic 1.8pf c parasitic 1.8pf r parasitic 3 r on 20 r on 20 r parasitic 3 figure 2. equivalent input circuit
LTC2273/ltc2272 23 22732f applications information input drive circuits input filtering a ? rst order rc lowpass ? lter at the input of the adc can serve two functions: limit the noise from input cir- cuitry and provide isolation from adc s/h switching. the LTC2273/ltc2272 have very broadband s/h circuits, dc to 700mhz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recom- mended rc ? lter. figures 3, 4a and 4b show three examples of input rc ? ltering at three ranges of input frequencies. in general, it is desirable to make the capacitors as large as can be toleratedthis will help suppress random noise as well as noise coupled from the digital circuitry. the LTC2273/ ltc2272 do not require any input ? lter to achieve data sheet speci? cations; however, no ? ltering will put more stringent noise requirements on the input drive circuitry. transformer coupled circuits figure 3 shows the LTC2273/ltc2272 being driven by an rf transformer with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase high frequency distortion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequen- cies below 1mhz. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 4a shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high frequency response and balance than ? ux coupled center tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. figure 4b shows the same circuit with components suitable for higher input frequencies. 0.1f a in + a in C 4.7pf 2.2f 4.7pf 4.7pf v cm LTC2273/ ltc2272 analog input 0.1f 0.1f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2f 22732 f04a 5 10 25 25 10 5 figure 4a. using a transmission line balun transformer. recommended for input frequencies from 100mhz to 250mhz 0.1f a in + a in C 2.2f 2.2pf 2.2pf v cm LTC2273/ ltc2272 analog input 0.1f 0.1f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2f 22732 f04b 5 25 25 5 figure 4b. using a transmission line balun transformer. recommended for input frequencies from 250mhz to 500mhz figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 5mhz to 150mhz 35 50 35 10 10 5 5 0.1f a in + a in C 8.2pf 2.2f 8.2pf 8.2pf v cm LTC2273/ ltc2272 t1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size except 2.2f 22732 f03
LTC2273/ltc2272 24 22732f applications information direct coupled circuits figure 5 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop ampli? er will de- grade the adc sfdr at high input frequencies. additionally, wideband op amps or differential ampli? ers tend to have high noise. as a result, the snr will be degraded unless the noise bandwidth is limited prior to the adc input. reference operation figure 6 shows the LTC2273/ltc2272 reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli? er and control circuit. the LTC2273/ltc2272 have three modes of reference operation: internal refer- ence, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in a full scale range of 2.25v p-p (pga = 0). a 1.25v output v cm is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f. the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and is not accessible for external use. the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference inputs. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1f (or larger) ceramic capacitor. pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.25v p-p ; pga = 1 selects an input range of 1.5v p-p . the 2.25v input range has the best snr; however, the distor- tion will be higher for input frequencies above 100mhz. for applications with high input frequencies, the low input range will have improved distortion; however, the snr will be 2.4db worse. see the typical performance characteristics section of this datasheet. figure 5. dc coupled input with differential ampli? er C C + + a in + a in C 2.2f 12pf 12pf v cm LTC2273/ ltc2272 analog input 22732 f05 cm amplifier = ltc6600-20, ltc1993, etc. high speed differential amplifier 25 25 1x or 2x 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2f tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 22732 f06 LTC2273/ltc2272 figure 6. reference circuit
LTC2273/ltc2272 25 22732f applications information 22732 f10 enc C enc + 3.3v 3.3v d0 q0 q0 LTC2273/ ltc2272 130 130 83 83 mc100lvelt22 figure 10. enc drive using a cmos to pecl translator figure 9. single-ended enc drive, not recommended for low jitter 22732 f09 enc C 1.6v v threshold = 1.6v enc + 0.1f LTC2273/ ltc2272 figure 7. a 2.25v range adc with an external 2.5v reference v cm sense 1.25v 3.3v 2.2f 2.2f 1f 22732 f07 LTC2273/ ltc2272 ltc6652-2.5 2, 3 6 4, 5, 7 ,8 figure 8a. equivalent encode input circuit figure 8b. transformer driven encode v dd v dd LTC2273/ltc2272 22732 f08a v dd enc C enc + 1.6v 1.6v 6k 6k to internal adc clock drivers 50 100 8.2pf 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 LTC2273/ ltc2272 22732 f08b enc C enc +
LTC2273/ltc2272 26 22732f applications information driving the encode inputs the noise performance of the LTC2273/ltc2272 can depend on the encode signal quality as much as for the analog input. the encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc oper- ating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies), take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude possible. if using trans- former coupling, use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a ? xed frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.4v to 3v. each input may be driven from ground to v dd for single-ended drive. maximum and minimum conversion rates the maximum conversion rate for the LTC2273 is 80msps. the maximum conversion rate for the ltc2272 is 65msps. the lower limit of the LTC2273/ltc2272 sample rate is determined by the pll minimum operating frequency of 20msps. for the adc to operate properly, the internal clk signal should have a 50% duty cycle. a duty cycle stabilizer cir- cuit has been implemented on chip to facilitate non-50% enc duty cycles. data format the msbinv pin selects the adc data format. a low level selects offset binary format (code 0 corresponds to Cfs, and code 65535 corresponds to +fs). a high level on msbinv selects 2s complement format (code C32768 corresponds to Cfs and code 32767 corresponds to +fs. shutdown modes the assertion of both shdn pins will shut down the adc and the serial interface and place the chip in a low-cur- rent mode. internal dither the LTC2273/ltc2272 are 16-bit adc with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 11, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted digitally from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off.
LTC2273/ltc2272 27 22732f applications information serialized data frame prior to serialization, the adc data is encoded into the 8b/10b format, which is dc balanced, and run-length limited. the receiver is required to lock onto the data and recover the clock with the use of a pll. the 8b/10b format requires that the adc data be broken up into 8-bit blocks (octets), which is encoded into 10-bit code groups applying the 8b/10b rules (refer to ieee std 802.3-2002 part 3, for a complete 8b/10b description). figure 12 illustrates the generation of one complete 8b/10b frame. the 8 most signi? cant bits of the adc are assigned to the ? rst half of the frame, and the remaining 8 bits to the second half of the frame. next, the two resulting octets are optionally scrambled and encoded into their corresponding 8b/10b code. finally, the two 10-bit code groups are serialized and transmitted beginning with bit 0 of code group 1. +C ain C ain + s/h amp digital summation 8b10b encoder multibit deep pseudo-random number generator 16-bit pipelined adc core precision dac clock/duty cycle control enc dither enable high = dither on low = dither off dith enc analog input 22732 f11 LTC2273/ltc2272 cmlout + cmlout C serializer figure 11. functional equivalent block diagram of internal dither circuit figure 12. evolution of one transmitted frame (compare to ieee std 802.3-2002 part 3, figure 36-3) bit 15 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 ha b c d e f g bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 ha b c d first octet adc output word msb lsb octet assignment optional scrambler 8b/10b encoder e f g bit 2 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 bit 1 cj h g f first scrambled octet 8b/10b code group 1 bit 0 of code group 1 is transmitted first i e d ab bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 hba c d e f g bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 hba c d second octet e f g bit 2 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 0 bit 1 chj g f second scrambled octet 8b/10b code group 2 i e d ab one frame serial out 22732 f12
LTC2273/ltc2272 28 22732f applications information initial frame synchronization in the absence of a frame clock, it is necessary to deter- mine the start of each frame through a synchronization process. to establish frame synchronization, figures 14 and 15 illustrate the following sequence: ? the receiver issues a synchronization request via the synchronization interface. ? if the synchronization request is active for more than one enc clock cycle, the LTC2273/ltc2272 will transmit a synchronization preamble. when the ismode pin is low the transmitted preamble will consist of consecu- tive k28.5 comma symbols in conformance with the jesd204 speci? cation. when the ismode pin is high, a series of idle ordered sets will be transmitted. the idle ordered sets consist of a k28.5 comma followed by either d5.6 or d16.2 as de? ned in ieee std 802.3-2002 part3, clause 36.2.4.12. ? the receiver searches for the expected preamble and waits for the correct reception of an adequate number of preamble characters. ? the receiver deactivates the synchronization request. ? upon detecting the deactivation of the synchronization request, the LTC2273/ltc2272 continue to transmit the synchronization preamble until the end of the frame. ? at the start of the next frame, the LTC2273/ltc2272 will begin transmitting data characters. ? the receiver designates the ? rst data character received after the preamble transmission to be the start of the frame. the ? rst octet of the frame contains the most signi? cant byte of the adcs output word. figure 13. timing relationship of analog sample to serial data out n C 6 n C 10 n C 9 n C 8 n C 1 n n C 5 n C 4 n + 3 n + 4 n C 9 n C 8 n C 7 n n + 1 t h t conv lat p t l t ap t bit n n + 1 n + 2 n + 8 n + 9 22732 f13 n + 10 analog input enc + internal parallel data internal 8b/10b data serial data out
LTC2273/ltc2272 29 22732f applications information figure 14a. sync + low transition to comma output timing (ismode is low) figure 14b. sync + high transition to data output timing (ismode is low) n C 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n C 10 n C 9 n C 8 n C 7 k28.5 (x2) k28.5 (x2) t conv t cs(max) lat sc t hd t cs(min) t su analog input enc + sync + serial data out 22732 f14a n C 1 n n + 1 n + 2 n + 3 n + 4 k28.5 (x2) k28.5 (x2) k28.5 (x2) n C 7 n C 6 t conv t cs(max) lat sd t hd t cs(min) t su analog input enc + serial data out 22732 f14b sync +
LTC2273/ltc2272 30 22732f sync request? start is ismode enabled? negative disparity? data transmission flow (see figure 18) transmit k28.5 as code group 1 wait for next frame clock transmit k28.5 as code group 2 transmit k28.5 as code group 1 transmit d5.6 as code group 2 transmit k28.5 as code group 1 transmit d16.2 as code group 2 no yes no yes no (disparity not ok) (negative disparity) (negative disparity) (disparity is ok) (positive disparity) (negative disparity) 22732 f15 yes applications information figure 15. initial synchronization flow diagram scrambling to avoid spectral interference from the serial data output, an optional data scrambler is added between the adc data and the 8b/10b encoder to randomize the spectrum of the serial link. the scrambler is enabled by setting the scram pin to a high logic level. the polynomial used for the scrambler is 1 + x 14 + x 15 , which is a pseudo-random pattern repeating itself every 2 15 C1. figure 16 illustrates the LTC2273/ltc2272 implementation of this polynomial in parallel form. the scrambled data is converted into two valid 8b/10b code groups, constituting a complete frame. the 8b/10b code groups are then serialized and transmitted. the receiver is required to deserializing the data, decode the code-groups into octets and descramble them back to the original octets using the self-aligning descrambler shown in figure 17. this descrambler is shown in 16-bit parallel form, which is an ef? cient implementation of the (1 + x 14 + x 15 ) polynomial, operating at the frame clock rate (adc sample rate).
LTC2273/ltc2272 31 22732f applications information figure 16. LTC2273/ltc2272 16-bit 1 + x 14 + x 15 parallel scrambler ss0 sample_clk d0 second octet from adc to 8b/10b encoder first octet second scrambled octet first scrambled octet ss1 d1 d2 qd c ff ss2 d3 ss3 ss4 d4 ss5 d5 d6 ss6 d7 ss7 sf0 d8 sf1 d9 d10 sf2 d11 sf3 sf4 d12 sf5 d13 d13 sf6 d15 msb sf7 msb qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff qd c ff 22732 f16
LTC2273/ltc2272 32 22732f applications information figure 17. required 16-bit 1 + x 14 + x 15 parallel descrambler frame_clk lsb d0 ss0 dq c ff d1 ss1 dq c ff d2 ss2 dq c ff d3 ss3 dq c ff d4 ss4 dq c ff d5 ss5 dq c ff d6 ss6 dq c ff d7 ss7 dq c ff d8 sf0 dq c ff d9 sf1 dq c ff d10 sf2 dq c ff d11 sf3 dq c ff d12 sf4 dq c ff d13 sf5 dq c ff d14 sf6 sf7 msb dq c ff d15 msb second scrambled octet from 8b/10b decoder descrambled adc data first scrambled octet 22732 f17
LTC2273/ltc2272 33 22732f applications information frame alignment monitoring after the initial synchronization has been established, it may be desirable to periodically verify that frame alignment is being maintained. the receiver may issue a synchroniza- tion request at any time, but data will be lost during the resynchronization interval. to verify frame alignment without the loss of data, frame alignment monitoring is enabled by setting the fam pin to a high level. in this mode, predetermined data in the second code group of the frame is substituted with the control character k28.7. the receiver is required to detect the k28.7 character and replace it with the original data. in this way, the second code group may be discerned from the ? rst, and the receiver is able to periodically verify the frame alignment without the loss of data (refer to table 1 and the ? ow diagram of figure 18). there are two frame alignment monitoring modes summarized in table 1. fam mode 1 is implemented when fam is high, and scram is low: ? when the data in the second code group of the current frame equals the data in the second code group of the previous frame, the LTC2273/ltc2272 will replace the second code group with the control character k28.7 before serialization. however, if a k28.7 symbol was already transmitted in the previous frame, the actual code group will be transmitted. ? upon receiving a k28.7 symbol, the receiver is required to replace it with the data decoded at the same position of the previous frame. fam mode 2 is implemented when fam is high and scram is high: ? when the data in the second code group of the current frame equals d28.7, the LTC2273/ltc2272 will replace this data with k28.7 before serialization. ? upon receiving a k28.7 symbol, the receiver is required to replace it with d28.7. with fam enabled the receiver is required to search for the presence of k28.7 symbols in the data stream. if two successive k28.7 symbols are detected at the same posi- tion other than the assumed end of frame, the receiver will realign its frame boundary to the new position. table 1. frame alignment monitoring modes scram pin ddsync pin action fam mode 1 low high the second code group is replaced with k28.7 if it is equal to the 2 nd code group of the previous frame fam mode 2 high high the second code group is replaced with k28.7 if it is equal to d28.7 fam off x low no k2 8 .7 substitutions will take place
LTC2273/ltc2272 34 22732f applications information table 2. sample rate ranges srr1 srr0 sample rate range 0 x 20msps < fs 35msps 1 0 30msps < fs 65msps 1 1 60msps < fs 80msps figure 18. data transmission flow diagram pll operation the pll has been designed to accommodate a wide range of sample rates. the srr0 and srr1 pins are used to con? gure the pll for the intended sample rate range. table 2 summarizes the sample clock ranges available to the user. serial test patterns to facilitate testing of the serial interface, three test patterns are selectable via pins pat0 and pat1. the available test patterns are described in table 3. a k28.5 comma may be used as a fourth test pattern by requesting synchronization through the sync + / sync C pins. is fam enabled? is scram enabled? is code group 2 = d28.7? transmit code group 1 transmit code group 2 transmit code group 2 transmit k28.7 as code group 2 no yes (frame alignment monitoring is enabled) (data scrambling is enabled) no yes no yes is code group 2 = code group 2 of last frame? transmit code group 2 no yes was k28.7 transmitted in last frame? transmit k28.7 as code group 2 transmit code group 2 no yes 22732 f18 transmit code group 1 generate 8b/10b code-groups 1 and 2 start scramble adc data if scram is enabled end table 3. test patterns pat1 pat0 test patterns 0 0 adc data 0 1 1010101010 pattern (8b/10b code group d21.5) 1 0 1+ x 9 + x 11 pseudo random pattern 1 1 1+ x 14 + x 15 pseudo random pattern
LTC2273/ltc2272 35 22732f applications information high speed cml outputs the cml outputs must be terminated for proper opera- tion. the ov dd supply voltage and the termination voltage determine the common mode output level of the cml outputs. for proper operation of the cml driver, the output common mode voltage should be greater than 1v. the directly-coupled termination mode of figure 19a is recommended when the receiver termination voltage is within the range of 1.2v to 3.3v. when the cml outputs are directly-coupled to the 50 termination resistors, the ov dd supply voltage serves as the receiver termination voltage, and the output common mode voltage will be approximately 200mv lower than ov dd . the directly-coupled differential termination of figure 19b may be used in the absence of a receiver termination voltage within the required range. in this case, the common mode voltage is shifted down to approximately 400mv below ov dd , requiring an ov dd in the range of 1.4v to 3.3v. if the serial receivers common mode input requirements are not compatible with the directly-coupled termination modes, the dc balanced 8b/10b encoded data will permit the addition of dc blocking capacitors as shown in figure 19c. in this ac-coupled mode, the termination voltage is determined by the receivers requirements. the coupling capacitors should be selected appropriately for the intended operating bit-rate, usually between 1nf to 10nf. in the ac- coupled mode, the output common mode voltage will be approximately 400mv below ov dd , so the ov dd supply voltage should be in the range of 1.4v to 3.3v. grounding and bypassing the LTC2273/ltc2272 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the LTC2273/ltc2272 have been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the LTC2273/ltc2272 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the LTC2273/ltc2272 are transferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible.
LTC2273/ltc2272 36 22732f applications information figure 19a. cml termination, directly-coupled mode (preferred) figure 19b. cml termination, directly-coupled differential mode 22732 f19a 50 50 50 50 data + data C gnd serial cml driver serial cml receiver 1.2v to 3.3v 50 transmission line 50 transmission line 16ma cmlout + ov dd cmlout C 22732 f19b 100 50 50 data + data C gnd serial cml driver serial cml receiver 1.4v to 3.3v 50 transmission line 50 transmission line 16ma cmlout + ov dd cmlout C
LTC2273/ltc2272 37 22732f applications information figure 19c. cml termination, ac-coupled mode 22732 f19c 50 50 0.01f 0.01f 50 50 data + data C gnd serial cml driver serial cml receiver 1.4v to 3.3v vterm 50 transmission line 50 transmission line 16ma cmlout + ov dd cmlout C
LTC2273/ltc2272 38 22732f typical applications silkscreen top top side
LTC2273/ltc2272 39 22732f typical applications inner layer 2 inner layer 3
LTC2273/ltc2272 40 22732f typical applications inner layer 4 inner layer 5
LTC2273/ltc2272 41 22732f typical applications bottom side silkscreen bottom
LTC2273/ltc2272 42 22732f typical applications cml adc assembly type u1 u3 data rate sample rate c1 c2, c3 l1 r5, r19 t3 input frequency dc1151a-c ltc2274cu tlk2501 1.5ghz to 2.5ghz 105msps 4.7pf 8.2pf 56nh 86.6 maba-007159 1mhz to 70mhz dc1151a-d ltc2274cu tlk2501 1.5ghz to 2.5ghz 105msps 1.8pf 3.9pf 18nh 43.2 wbc1-1lb 70mhz to 140mhz dc1151a-e LTC2273cu tlk2501 1.5ghz to 2.5ghz 80msps 4.7pf 8.2pf 56nh 86.6 maba-007159 1mhz to 70mhz dc1151a-f LTC2273cu tlk2501 1.5ghz to 2.5ghz 80msps 1.8pf 3.9pf 18nh 43.2 wbc1-1lb 70mhz to 140mhz dc1151a-g ltc2272cu tlk1501 0.6ghz to 1.5ghz 65msps 4.7pf 8.2pf 56nh 86.6 maba-007159 1mhz to 70mhz dc1151a-h ltc2272cu tlk1501 0.6ghz to 1.5ghz 65msps 1.8pf 3.9pf 18nh 43.2 wbc1-1lb 70mhz to 140mhz j8 clkout 22732 ta02 u1 ltc2272cuj/LTC2273cuj gnd gnd gnd gnd gnd gnd gnd gnd ognd ognd ognd ognd gnd tp3 ext ref famon 1 3 31 scram 34 msbinv 36 pat1 33 pat0 32 dith 15 ismode 16 pll0 17 pll1 18 pdadc 19 pdser fam scram msbinv pat1 pat0 dith ismode pll0 pll1 pdadc pdser 20 enc C 10 enc + 9 sense 38 v cm 39 pga v cm pga 35 a in C 5 a in + 4 1 2 3 5 4 sync + 28 sync C 29 cmlout C 23 cmlout + 24 2 6 12 7 13 811143740 22 21 v dd v dd v dd v dd ov dd ov dd 3.3v 3.3v 2.5v ov dd 25 26 27 30 gnd 41 c13 0.1f c26 0.1f l4 ferrite bead blm1866470sn1d c12 0.1f c14 0.01f c26a 1nf c27a 1nf c32 0.01f c15 0.01f r1 10 r18 1000 l1* r2 10 r16 10 t3* t1 mabaes0060 t2 maba-007159-000000 r17 10 r15 optional c1* r6 100 r3 68.1 r4 68.1 1 2 3 5 4 c16 202f c20 0.01f c6 0.1f 3 2 1 4 5 r9 4.99 r10 4.99 c8 8.2pf r7 4.99 r8 4.99 c11 0.1f c4 0.1f r11 100 ? ? ? ? ? ? c9 0.1f c10 0.1f r51 68.1 r52 68.1 r19* c3* c2* r5* j2 sig in j5 encode c5 0.1f r34 34 sum sbtc-2-10l+ port1 nc port2 gnd gnd 3 1 4 2 2 3.3v 3.3v 2.5v v dd sense r55 optional r56 0 tp4 gnd 5 6 4 3 12 gnd nc7svu04p5x nc7sp17p5x sw1 main sync evqppda25 v cc 35 r35 49.9 r33 10k r32 10k c30 0.1f in lt1763cde out in byp 11 shdn 8 nc 1 nc 4 nc 9 nc 12 10 6 2 out 3 sense 5 713 r36 10k r22 1000 r31 4.32k c18 10f 0805 c17 4.7f 0805 c19 0.01f in lt1763cde-2.5 out in byp gnd gp gnd gp 11 shdn 8 nc 1 nc 4 nc 9 nc 12 10 6 2 out 3 sense 5 713 r11 10k c33 10f 0805 2.5v ov dd ov dd c34 0.01f l3 ferrite bead blm1866470sn1d adc 3.3v 3.3v ex_3.3v tp1 ex_3.3v tp2 gnd *u3 tx_en 51 20 loopen 21 tx_er 22 v dd 23 enable 24 lckrefn 25 prbsen 26 testen 27 gnd 28 rx_er/prbs_pass 29 rx_dv/los 30 dinrxp 54 dinrxn 53 gnda 52 rxd0 50 rxd1 49 rxd2 48 v dd 47 rxd3 46 rxd4 45 rxd5 44 rxd6 43 gnd 42 rxd7 41 rx_clk 40 rxd8 39 rxd9 38 v dd 37 rxd10 36 rxd11 35 rxd12 34 rxd13 33 gnd 32 rxd14 31 rxd15 pbus0 pbus1 pbus2 pbus3 pbus4 pbus5 pbus6 pbus7 pbus8 pbus9 pbus10 pbus11 pbus12 pbus13 pbus14 pbus15 r23b 33 r23c 33 r24a 33 r24b 33 r24c 33 r24d 33 r23d 33 r25a 33 r25b 33 r25c 33 r25d 33 r26a 33 r26b 33 r27c 33 r27d 33 r26c 33 r26d 33 c36 0.01f v dda 57 r ref 56 v dda 55 douttxp 60 douttxn 59 gnda 58 gnda 61 j7 cmlout + c26b 1nf c27b 1nf j6 cmlout C r20 200 r12 49.9k r13 49.9k r21 825 c21 0.01f c22 0.01f txd0 62 txd1 63 txd2 64 v dd 1 txd3 2 txd4 3 txd5 4 gnd 5 txd6 6 txd7 7 gtx_clk 8 v dd 9 txd8 10 txd9 11 txd10 12 gnd 13 txd11 14 txd12 15 txd13 16 txd14 17 gnd 18 txd15 19 dith 1 off ismode 2 pll0 3 pll1 4 8765 pdadc 1 off pdser 2 fam 3 scram 4 8765 pat0 1 off s2 s3 s4 pat1 2 pga 3 msbinv 4 8765 l2 ferrite bead blm1866470sn1d c23 0.01f c25 0.01f c24 0.01f d2 data good jp2 run shdn r44 1k r14 33.2 3.3v int_sync sync optional c nc7sz332psx a yb 4 6 3 v cc gnd 52 1 c28 0.01f 4 2 r32 10 c25 0.01f r43 10k r46 10k r28 825 r29 825 d1 sync err c37 0.01f 2.5v 1 3 2 pfc8574ts a0 6 a1 7 a2 9 scl 2 sda scl sda 3.3v 4 int 1 nc 3 nc 8 nc 13 nc 18 v ss 15 pat0 20 pat1 19 pga 17 msbinv 16 pdadc 14 pdser 12 fam 11 scram 10 p7 p6 p5 p4 p3 p2 p1 p0 v dd 5 pfc8574ts a0 6 a1 7 a2 9 scl 2 sda scl sda 3.3v 3.3v 4 int 1 nc 3 nc 8 nc 13 nc 18 v ss 15 20 19 17 rx_er 16 pll1 14 pll0 12 ismode 11 dith 10 p7 p6 p5 p4 p3 p2 p1 p0 v dd 5 3.3v header optional 12 10 14 8 6 4 2 pat1 pat0 pga scram fam pdser pdadc sync int_sync msbinv dith ismode pll0 pll1 11 9 13 7 5 3 1 r53 1k r54 optional 21 19 17 15 13 11 9 7 5 3 1 41 39 37 35 33 31 29 27 25 23 61 59 57 55 53 51 49 47 45 43 81 79 77 75 73 71 69 67 65 63 99 97 95 93 91 89 87 85 83 22 20 18 16 14 12 10 8 6 4 2 42 40 38 36 34 32 30 28 26 24 62 60 58 56 54 52 50 48 46 44 82 80 78 76 74 72 70 68 66 64 100 pbus8 98 96 94 92 90 88 86 pbus5 pbus6 pbus7 pbus14 rx_er pbus15 pbus0 pbus1 pbus2 pbus3 pbus4 pbus9 pbus10 pbus11 pbus12 pbus13 84 2.5v r47 optional r45 10k nc7wb66k8x 1b 2b gnd v cc 1a 1 oe1 7 2a 5 oe2 36 2 sda scl 4 8 r48 optional r49 optional r39 1000 r50 optional 3.3v 2.5v 3.3v 24lc025-i/st wp a0 v ss v cc a2 a1 1 4 8 sda scl sda scl 7 3 2 5 6 24lc32a-i/st wp a0 v ss v cc a2 a1 1 4 8 sda scl wp sda scl 7 3 2 5 6 wp c35 0.01f r37 4750 r38 4750 r40 4750 82pf *version table
LTC2273/ltc2272 43 22732f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) 6.00 p 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 s 45 o chamfer 0.40 p 0.10 40 39 1 2 bottom viewexposed pad 4.50 ref (4-sides) 4.42 p 0.10 4.42 p 0.10 4.42 p 0.05 4.42 p 0.05 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p 0.05 4.50 p 0.05 (4 sides) 5.10 p 0.05 6.50 p 0.05 0.25 p 0.05 0.50 bsc package outline r = 0.10 typ
LTC2273/ltc2272 44 22732f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 1208 ? printed in usa related parts part number description comments ltc1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain ltc1994 low noise, low distortion fully differential input/ output ampli? er/driver low distortion: C94dbc at 1mhz ltc2215 16-bit, 65msps, low noise adc 700mw, 81.5db snr, 100db sfdr, 64-pin qfn ltc2216 16-bit, 80msps, low noise adc 970mw, 81.3db snr, 100db sfdr, 64-pin qfn ltc2217 16-bit, 105msps, low noise adc 1190mw, 81.2db snr, 100db sfdr, 64-pin qfn ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 140mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2203 16-bit, 25msps, 3.3v adc, lowest noise 220mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2204 16-bit, 40msps, 3.3v adc 480mw, 79db snr, 100db sfdr, 48-pin qfn ltc2205 16-bit, 65msps, 3.3v adc 590mw, 79db snr, 100db sfdr, 48-pin qfn ltc2206 16-bit, 80msps, 3.3v adc 725mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2207 16-bit, 105msps, 3.3v adc 900mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.7db snr, 100db sfdr, 64-pin qfn ltc2209 16-bit, 160msps, adc, lvds outputs 1.45w, 77.1db snr, 100db sfdr, 64-pin qfn ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2249 14-bit, 80msps adc 230mw, 73db snr, 5mm 5mm qfn package ltc2250 10-bit, 105msps adc 320mw, 61.6db snr, 5mm 5mm qfn package ltc2251 10-bit, 125msps adc 395mw, 61.6db snr, 5mm 5mm qfn package ltc2252 12-bit, 105msps adc 320mw, 70.2db snr, 5mm 5mm qfn package ltc2253 12-bit, 125msps adc 395mw, 70.2db snr, 5mm 5mm qfn package ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 5mm 5mm qfn package ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2274 16-bit, 105msps, serial adc 1.3w, 100db sfdr, high speed serial interface (jesd204), 6mm 6mm qfn package ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2299 dual 14-bit, 80msps adc 230mw, 71.6db snr, 5mm x 5mm qfn package ltc5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer ltc5515 1.5 ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator ltc5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 single-ended rf and lo ports ltc5527 400mhz to 3.7ghz high signal level downconverting mixer 4.5v to 5.25v supply, 23.5dbm iip3 at 1900mhz, i cc = 78ma, conversion gain = 2db ltc5579 1.5ghz to 3.8ghz high linearity upconverting mixer 3.3v supply, 27.3dbm oip3 at 2.14ghz, conversion gain = 2.6db at 2.14ghz ltc6400-20 1.8ghz low noise, low distortion differential adc driver for 300mhz if fixed gain 10v/v, 2.1nv hz total input noise, 3mm 3mm qfn-16 package

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